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6-Weeks Summer Training on VLSI Design

6-Weeks Summer Training on VLSI Design

By MUKESH SUKLA Categories: ASIC Design
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About Course

This program will enable the students to learn RTL design methodologies and testbench-based verification process. Also, they will learn design constraints and will perform the synthesis to realize the gate-level netlist.

The generated netlist will be implemented using learner kit and can drive the proof-of-concept (PoC)

What Will You Learn?

  • Digital Logic Design
  • Verilog HDL for Designers
  • Verilog for Verification
  • Design Constraints
  • Logic Synthesis
  • Scripting for VLSI Engineers

Course Content

Module-0: RCVI and Circuit Fundamentals

Module-1: Digital Fundamentals-I

Module-2: Introduction to Verilog HDL for Logic Designers

Module-3: Digital Fundamentals-II

Module-4: Verilog HDL for Logic Verification

Module-5: Advanced Design Blocks for ASIC Design

Module-6: Advanced Design Constructs of Verilog HDL

Module-7: Design Constraints (SDC Fundamentals)

Module-8: Logic Synthesis Process (ASIC)

Module-9: Introduction to Protocols

Module-10: Quality of Report (QoR)

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