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6-Days Workshop on Digital Design using Verilog HDL

10

40h

By MUKESH SUKLA In Workshops

VLSI Design Engineer – I

31

100h

By MUKESH SUKLA In ASIC Design

₹499.00 ~~₹2,499.00~~

4-Weeks Winter Training on RTL Design

26

100h

By MUKESH SUKLA In Digital

₹299.00 ~~₹499.00~~

65% Booked

Bootcamp Program on Digital Design using Verilog HDL

75

12h

By MUKESH SUKLA In ASIC Design

₹249.00 ~~₹499.00~~

38% Booked

4-Weeks Winter Internship on Protocol Design and Verification

0

100h

By MUKESH SUKLA In Digital

₹499.00 ~~₹1,499.00~~

0% Booked

Enrollment is now closed

Design Verification using System Verilog

4

150h

By MUKESH SUKLA In ASIC Design

₹999.00 ~~₹1,500.00~~

Design Verification using UVM

2

100h

By MUKESH SUKLA In Digital

₹499.00 ~~₹1,000.00~~

5.00

(2)

TCL Script for VLSI Engineers

30

By MUKESH SUKLA In Programming and Scripting

₹249.00 ~~₹999.00~~

Linux and Shell Scripting for VLSI Engineers

19

40h

By MUKESH SUKLA In Programming and Scripting

₹249.00 ~~₹499.00~~

5.00

(1)

C PROGRAMMING FOR VLSI ENGINEERS

10

45h

By MUKESH SUKLA In Programming and Scripting

₹149.00 ~~₹499.00~~

Circuit Design and Verification Engineer – I

4

By MUKESH SUKLA In ASIC Design

₹499.00 ~~₹1,250.00~~

Integrated Diploma in VLSI Design (IDVD)

18

By MUKESH SUKLA In ASIC Design

₹499.00 ~~₹999.00~~

6-Weeks Summer Training on VLSI Design

0

250h

By MUKESH SUKLA In ASIC Design

₹9,500.00

0% Booked

MNDCS-2026 Invited Talk

0

2h

By MUKESH SUKLA In Workshops

Python for VLSI Engineers – A Journey towards Automation

22

72h

By MUKESH SUKLA In Programming and Scripting

₹99.00 ~~₹1,000.00~~

Training on VLSI Circuits and PCB Design

27

36h

By MUKESH SUKLA In Analog and Mixed Signal

₹249.00 ~~₹499.00~~

Advanced RTL Design and Verification using System Verilog (Level-1)

0

200h

By MUKESH SUKLA In ASIC Design, Workshops

₹11,800.00 ~~₹15,000.00~~

2-WEEKS WORKSHOP ON ADVANCE RTL DESIGN AND VERIFICATION

7

By MUKESH SUKLA In Workshops

₹249.00 ~~₹1,000.00~~

6-Days Workshop on Design Verification using System Verilog and FPGA Validation

16

40h

By MUKESH SUKLA In Workshops

₹149.00 ~~₹499.00~~

Enrollment is now closed

IETE Sponsored 6-Days Workshop on VLSI Circuits and PCB Design (Hybrid)

0

36h

By MUKESH SUKLA In Workshops

₹149.00 ~~₹500.00~~

VLSI Sample Test (VST) Series

35

By MUKESH SUKLA In Core Engineering

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MUKESH SUKLA

Biography

Courses

6-Days Workshop on Digital Design using Verilog HDL

VLSI Design Engineer – I

4-Weeks Winter Training on RTL Design

Bootcamp Program on Digital Design using Verilog HDL

4-Weeks Winter Internship on Protocol Design and Verification

Design Verification using System Verilog

Design Verification using UVM

TCL Script for VLSI Engineers

Linux and Shell Scripting for VLSI Engineers

C PROGRAMMING FOR VLSI ENGINEERS

Circuit Design and Verification Engineer – I

Integrated Diploma in VLSI Design (IDVD)

6-Weeks Summer Training on VLSI Design

MNDCS-2026 Invited Talk

Python for VLSI Engineers – A Journey towards Automation

Training on VLSI Circuits and PCB Design

Advanced RTL Design and Verification using System Verilog (Level-1)

2-WEEKS WORKSHOP ON ADVANCE RTL DESIGN AND VERIFICATION

6-Days Workshop on Design Verification using System Verilog and FPGA Validation

IETE Sponsored 6-Days Workshop on VLSI Circuits and PCB Design (Hybrid)

VLSI Sample Test (VST) Series

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MUKESH SUKLA

Biography

Courses

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