About Course
This program will cover the design verification and the major difference between testbench-based and class-based verification. We will discuss the basic syntax of system Verilog and creating the complete environment for any protocol verification using SV constructs. One standard protocol will be discussed and students will be able to extract the test features and can develop the test plan. Debugging and bug fixing techniques will be covered with real-time implementation.
Course Content
Module#1:
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M1-0: Introduction to VLSI Design and Roles
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M1-1: Introduction to Verilog HDL Fundamentals
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M1-2: Operators and Logic Design using Operators
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M1-3: Datatypes
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M1-4: Digital Blocks using Dataflow Model
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M1-5: Quartus Tool Flow – Functional Simulation
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M1-6: Cadence Flow: Functional Simulation
Module#2:
Module#3:
Module#4:
Protocol Fundamentals and Implementation
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