4-Weeks Winter Training on RTL Design

Module M-2: Module#2: Logic Verification and Functional Simulation

• L-1[M2-1] Verilog for Verification: Testbench Fundamentals
• L-2[M2-2] Verilog for Verification: Advance Constructs using Loops
• L-3[M2-3] Procedures and Execution of Statements
• L-4[M2-4] Tasks and Functions
• L-5[M2-5] Module-based Verification

Module M-3: Module#3: CAD Environment Development and Debugging Process

• L-1[M3-1] Quartus Tool Flow
• L-2[M3-2] Simulation using EDA Playground
• L-3[M3-3] Cadence Xcelium Environment
• L-4[M3-4] Linux Basics for VLSI Engineers

Module M-4: Module#4: Protocol Fundamentals and Implementation

• L-1[M4-1] Protocols and Standards
• L-2[M4-2] Block-level Implementation of standard protocols
• L-3[M4-3] Specification, Project Document and RTL Implementation
• L-4[M4-4] Functional Verification
• L-5[M4-5] Design Constraint
• L-6[M4-6] Logic Synthesis

Module M-5: Design Specifications

• L-1FIFO