About Course
The learners will be able to build the architecture and micro-architecture at block-level and sub-block level with complex functionalities. He/she will be understanding the digital logic design like control blocks, data path, memory. They will have a strong understanding of Verilog-HDL and the best practices to implement designs using synthesizable Verilog constructs. They will be solving problems with creative ideas with algorithmic level, structural level and switch level models. Also, they can perform delay simulations using gate delay models.
Course Content
Module#1: Digital Fundamentals and RTL Implementation
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[M0] Introduction to Semiconductor Design Process and Oppurtunities
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[M1-1] Digital Design Fundamentals and Implementation using Verilog HDL
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[M1-2] Verilog Models: Data Flow and Operators
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[M1-3] Verilog HDL Data Types
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[M1-4] Digital Design: Combinational Design and Basic Building Blocks
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[M1-5] Verilog Models: Structural Model and Primitives
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[M1-6] Sequential Logic Design
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[M1-7] Verilog Models: Behavioural Model
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[M1-8] FSM Fundamentals and RTL Implementation
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[M1-9] Functions
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[M1-10] Switch Level Implementation
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[M1-11] Architecture and Micro-architecture
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[M1-12] Processor Architecture – Register and ALU Implementation
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[M1-13] Synthesis Basics
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[M1-14] Quality of Report – PPA
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Assignment#1
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Assignment#2
Module#2: Logic Verification and Functional Simulation
Module#3: CAD Environment Development and Debugging Process
Module#4: Protocol Fundamentals and Implementation
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