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6-Days Workshop on Design Verification using System Verilog and FPGA Validation

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6-Days Workshop on Design Verification using System Verilog and FPGA Validation

About The Course

This workshop will enable the learners with

  • System Verilog Fundamentals for Verification
  • Concepts of Design Verification
  • FPGA Validation Process
The Course Curriculam

D-1: Introduction to Design Verification

  • Introduction
  • System Verilog Fundamentals
  • Data types
  • Introduction to Design and Verification
  • SystemVerilog Fundamentals and Verification Constructs
  • Module and Testbench

D-2: Control Flow and Loops

D-3: OPPs Basics

D-4: Verification Environment – A Case Study using Synchronous D-FF

D-5: Design under Test and Models

D-6: ASIC Design Flow and FPGA Validation Process

03 MUKESH_KUMAR_SUKLA

MUKESH SUKLA

Semiconductor Expert

Ph.D., M. Tech, B.Tech/ Experience (s): 20 Years

14 Courses 199 Students
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