About Course
This workshop will enable the learners with
- System Verilog Fundamentals for Verification
- Concepts of Design Verification
- FPGA Validation Process
Course Content
D-1: Introduction to Design Verification
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Introduction
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System Verilog Fundamentals
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Data types
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Introduction to Design and Verification
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SystemVerilog Fundamentals and Verification Constructs
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Module and Testbench
D-2: Control Flow and Loops
D-3: OPPs Basics
D-4: Verification Environment – A Case Study using Synchronous D-FF
D-5: Design under Test and Models
D-6: ASIC Design Flow and FPGA Validation Process
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