
Powering up

Powering up
<p>This workshop will enable the learners with</p><ul><li>System Verilog Fundamentals for Verification</li><li>Concepts of Design Verification</li><li>FPGA Validation Process</li></ul>
Module M-1: D-1: Introduction to Design Verification
Module M-2: D-2: Control Flow and Loops
Module M-3: D-3: OPPs Basics
Module M-4: D-4: Verification Environment - A Case Study using Synchronous D-FF
Module M-5: D-5: Design under Test and Models
Module M-6: D-6: ASIC Design Flow and FPGA Validation Process
MUKESH SUKLA