Powering up
Powering up
<p>This program will enable the students to learn RTL design methodologies and testbench-based verification process. Also, they will learn design constraints and will perform the synthesis to realize the gate-level netlist.</p><p>The generated netlist will be implemented using learner kit and can drive the proof-of-concept (PoC)</p>
Module M-1: Module-0: RCVI and Circuit Fundamentals
Module M-2: Module-1: Digital Fundamentals-I
Module M-3: Module-2: Introduction to Verilog HDL for Logic Designers
Module M-4: Module-3: Digital Fundamentals-II
Module M-5: Module-4: Verilog HDL for Logic Verification
Module M-6: Module-5: Advanced Design Blocks for ASIC Design
Module M-7: Module-6: Advanced Design Constructs of Verilog HDL
Module M-8: Module-7: Design Constraints (SDC Fundamentals)
Module M-9: Module-8: Logic Synthesis Process (ASIC)
Module M-10: Module-9: Introduction to Protocols
Module M-11: Module-10: Quality of Report (QoR)
Module M-12: Work Book v2p0
Module M-13: Project#1: Digi_Clock_v1p2
Module M-14: Memory_Blocks
MUKESH SUKLA