Advanced RTL Design and Verification using System Verilog (Level-1)

About Course

This course will enable the students to understand the building blocks of any digital system. The combinational blocks and sequentional blocks are implemented using verilog HDL and verified.

Course Content

Module#1: RCVI Fundamentals and Circuit Fundamentals

[M-1.1] Introduction to IC Design and Roles
[M-1.2] Semiconductor Basics
[M-1.3] Circuit Analysis
[M-1.4] Netlist and Simulation Fundamentals
[M-1.5] CMOS Circuits
[M-1.6] Parasitics and Circuit Performance Analysis

Module#2: Digital System Fundamentals-I (Combinational Blocks)

Module#3: Digital System Fundamentals – II (Sequential Blocks)

[M-3.1] Sequential Logic Design Fundamentals
[M-3.2] Latch and FF Basics
[M-3.3] Signals and Timing Analysis – Synchronous and Asynchronous Operations
[M-3.4] Advanced Design Methods: Finite State Machines (FSMs)
[M-3.5] Counters and Frequency Dividers
[M-3.6] Registers
[M-3.7] Memory (ROM/ RAM) Operations and Design
[M-3.8] Control, Sequence Detector and Sequence Generators
[M-3.9] LFSR
[M-3.10] Code Converters

Module#4: System Verilog Fundamentals

Module#5: Design Verification using System Verilog Constructs

Module#6: Design Specification Review and Protocol Basics

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Advanced RTL Design and Verification using System Verilog (Level-1)

About Course

What Will You Learn?

Course Content

Module#1: RCVI Fundamentals and Circuit Fundamentals

[M-1.1] Introduction to IC Design and Roles

[M-1.2] Semiconductor Basics

[M-1.3] Circuit Analysis

[M-1.4] Netlist and Simulation Fundamentals

[M-1.5] CMOS Circuits

[M-1.6] Parasitics and Circuit Performance Analysis

Module#2: Digital System Fundamentals-I (Combinational Blocks)

[M-2.1] Introduction to Digital Systems

[M-2.1] Binary Codes and Data

[M-2.3] Logic Gates, Boolean Operators and Industrial Applications

[M-2.4] Logic Optimization and Implementation Techniques

[M-2.5] Basic Building Blocks – Multiplexer, De-Multiplexer, Decoder and Encoder

[M-2.6] Control Functions and Arithmetic Circuits

Module#3: Digital System Fundamentals – II (Sequential Blocks)

[M-3.1] Sequential Logic Design Fundamentals

[M-3.2] Latch and FF Basics

[M-3.3] Signals and Timing Analysis – Synchronous and Asynchronous Operations

[M-3.4] Advanced Design Methods: Finite State Machines (FSMs)

[M-3.5] Counters and Frequency Dividers

[M-3.6] Registers

[M-3.7] Memory (ROM/ RAM) Operations and Design

[M-3.8] Control, Sequence Detector and Sequence Generators

[M-3.9] LFSR

[M-3.10] Code Converters

Module#4: System Verilog Fundamentals

[M-4.1] Introduction to Verification and System Verification Language

[M-4.2] Creating a Verification Plan, Extracting Features and Debugging Process

[M-2.3] Datatypes

[M-4.4] Arrays in SV

[M-4.5] Control Flow: Loops, Tasks, and Functions

[M-4.6] Process Flow

Module#5: Design Verification using System Verilog Constructs

[M-5.1] Object-Oriented Programming (OOPs) Fundamentals

[M-5.2] Deep Copy and Shallow Copy

[M-5.3] Casting

[M-5.4] Constraints and Randomization

[M-5.5] System Verilog callback

Module#6: Design Specification Review and Protocol Basics

[M-6.1] System Design and Architectures

[M-6.2] Processor Fundamentals

[M-6.3] ASIC Solutions for Image Signal Processing Fundamentals

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