Advanced RTL Design and Verification using System Verilog (Level-1)

Module M-3: Module#3: Digital System Fundamentals - II (Sequential Blocks)

• L-1[M-3.1] Sequential Logic Design Fundamentals
• L-2[M-3.2] Latch and FF Basics
• L-3[M-3.3] Signals and Timing Analysis - Synchronous and Asynchronous Operations
• L-4[M-3.4] Advanced Design Methods: Finite State Machines (FSMs)
• L-5[M-3.5] Counters and Frequency Dividers
• L-6[M-3.6] Registers
• L-7[M-3.7] Memory (ROM/ RAM) Operations and Design
• L-8[M-3.8] Control, Sequence Detector and Sequence Generators
• L-9[M-3.9] LFSR
• L-10[M-3.10] Code Converters

Module M-4: Module#4: System Verilog Fundamentals

• L-1[M-4.1] Introduction to Verification and System Verification Language
• L-2[M-4.2] Creating a Verification Plan, Extracting Features and Debugging Process
• L-3[M-2.3] Datatypes
• L-4[M-4.4] Arrays in SV
• L-5[M-4.5] Control Flow: Loops, Tasks, and Functions
• L-6[M-4.6] Process Flow

Module M-5: Module#5: Design Verification using System Verilog Constructs

• L-1[M-5.1] Object-Oriented Programming (OOPs) Fundamentals
• L-2[M-5.2] Deep Copy and Shallow Copy
• L-3[M-5.3] Casting
• L-4[M-5.4] Constraints and Randomization
• L-5[M-5.5] System Verilog callback

Module M-6: Module#6: Design Specification Review and Protocol Basics

• L-1[M-6.1] System Design and Architectures
• L-2[M-6.2] Processor Fundamentals
• L-3[M-6.3] ASIC Solutions for Image Signal Processing Fundamentals