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Advanced RTL Design and Verification using System Verilog (Level-1)

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Advanced RTL Design and Verification using System Verilog (Level-1)

About The Course

This course will enable the students to understand the building blocks of any digital system. The combinational blocks and sequentional blocks are implemented using verilog HDL and verified.

What Will You Learn?

Circuit Fundamentals for IC Designers and Simulation Basics

Digital System Design Understanding

System Verilog for Design

System Verilog for Verification

Design Verification Process

Protocol Fundamentals

The Course Curriculam

Module#1: RCVI Fundamentals and Circuit Fundamentals

  • [M-1.1] Introduction to IC Design and Roles
  • [M-1.2] Semiconductor Basics
  • [M-1.3] Circuit Analysis
  • [M-1.4] Netlist and Simulation Fundamentals
  • [M-1.5] CMOS Circuits
  • [M-1.6] Parasitics and Circuit Performance Analysis

Module#2: Digital System Fundamentals-I (Combinational Blocks)

Module#3: Digital System Fundamentals – II (Sequential Blocks)

Module#4: System Verilog Fundamentals

Module#5: Design Verification using System Verilog Constructs

Module#6: Design Specification Review and Protocol Basics

03 MUKESH_KUMAR_SUKLA

MUKESH SUKLA

Semiconductor Expert

Ph.D., M. Tech, B.Tech/ Experience (s): 20 Years

14 Courses 199 Students
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