The boot-camp program is designed for 3^rd year and 4^th year graduates of ECE/ ELE/ EE/ EIE and/or self-motivated semiconductor aspirants to have the foundation knowledge in digital design and developing solutions for application-specific integrated circuits (ASICs). Learners will be able to learn the industrial design approach to solve some communication problems. Verilog HDL will be discussed to write the industry standard RTL codes and essential guidelines for making them synthesize. Learners will be familiar with the RTL design roles and will be able to appropriately decide to chose FSM-based logic implementation, structural and algorithmic implementation.

Learners will be able to write the testbench to verify the functionalities at the block-level. Also the timing delay can be used to perform the initial timing simulations and can perform the setup and hold check. The open source platforms will be used to perform the code compilation and simulation.