Design Verification using System Verilog and Protocol Fundamentals

Module M-2: Fundamentals of System Verilog

• L-1Fundamentals of System Verilog
• L-2M1P2: Introduction to System Verilog Fundamentals (r2.0)
• Q-1System Verilog Fundamentals

Module M-3: Data Types and Arrays

• L-1Data Types and Arrays
• L-2M1P4: Data Types (r2.0)
• L-3Data Types and Literals (PART-2)
• Q-1Data Types and Arrays
• L-4M1P5: System Verilog Array (r2.0)
• L-5M1P6: Tasks and Functions (r2.0)
• L-6Practice Code: Array (r2.0)

Module M-4: Flow Control and Blocking Non-Blocking Assignments

• L-1Flow Control and Blocking and Non-Blocking Assignments in SV
• L-2M1P7: System Verilog Control Flow (r2.0)
• Q-1Flow Control and Blocking Non-Blocking Assignment

Module M-5: Tasks and Functions

• L-1Tasks and Functions
• Q-1Task and Function

Module M-6: Processes

• L-1SV Processes
• Q-1SV Processess

Module M-7: Interprocess Communication

• L-1Interprocess Communication
• Q-1Interprocess Communication

Module M-8: OOPs Concepts

• L-1OOPs Concepts
• Q-1OOPs Concept

Module M-9: Casting

• L-1Casting
• Q-1Casting in SV

Module M-10: Randomization and Constraints

• L-1Randomization and Constraints
• Q-1Randomization and Constraints

Module M-11: A Case Study: Synchronous DFF

• L-1DV Environment for Synchronous DFF

Module M-12: Protocol Verification

• L-1APB Design and Verification