About Course
Trainees will be able to learn the fundamentals of system verilog language syntax and can develop a stable environment for any block-level verification. Also, he/she will be having a good understanding about a communication protocol, preparing a test plan by extracting the features.
Course Content
Module#1: Introduction
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[M1-1] Introduction to Chip Verification Process
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[M1-2] Fundamentals of System Verilog
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[M1-3] Design Verification Process
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[M1-4] Datatypes
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[M1-5] Literals
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[M1-6] Operators
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[M1-7] Case Studies
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[M1-8] System Verilog Arrays
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[M1-9] Task and Function
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[M1-10] Control Flow
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A-1: Dtatatypes
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A-2: System Verilog Array
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A-3: System Verilog Task and Function
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A-4: SystemVerilog Control flow, blocking and nonblocking
Module#2: System Verilog Process
Module#3: Verification and Testbench Fundamentals
Module#4: Case Study
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