System Verilog and Protocol Verification

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System Verilog and Protocol Verification

By MUKESH SUKLA Categories: ASIC Design
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About Course

This program is designed for the key enthusiastic semiconductor learners who wants to build a career in semiconductor design and manufacturing.

You can be able to

¬Know the digital fundamentals

¬Apply the concepts to solve the problems

¬Learn the verification process

¬Strong knowledge about System Verilog Language

¬Creating a SV environment for a protocol

¬Understand an interface protocol

What Will You Learn?

  • System Verilog Fundamentals
  • Language and Syntax
  • Use cases and Applications
  • Parts of SV-based verification environment
  • How to create a stable environment
  • Protocol understanding
  • Verification Plan and test case development
  • Verification Run
  • Debugging and Report Preparation
  • Verification Sign-Off

Course Content

Module#1: System Verilog Language and Design Verification Constructs

  • [M1-1] Introduction
  • [M1-2] System Verilog Fundamentals
  • [M1-3] Introduction to Design Verification
  • [M1-4] Datatypes
  • [M1-5] Literals
  • [M1-6] Operators
  • [M1-7] Case Studies
  • [M1-8] Array
  • [M1-9] Functions and Tasks
  • [M1-10] Control Flow
  • Use Case#1
  • Quiz-1: Fundamentals

Module#2: System Verilog Language and Design Verification Constructs

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