2-WEEKS WORKSHOP ON ADVANCE RTL DESIGN AND VERIFICATION

Module M-4: D2-1: Testbench-Based Verification

• L-1Testbench Fundamentals

Module M-5: D2-2: Design Verification using Intel Quartus Flow

• L-1Design Verification using Intel Quartus

Module M-6: D2-3: System Verilog for Verification

• L-1System Verilog for Verification

Module M-7: D3-1: RTL Design using Behavioral Model

• L-1RTL Design using Behavioral Model

Module M-8: D3-2: Data Types in System Verilog

• L-1Data Types in SV

Module M-9: D4-1: Tasks and Functions

• L-1Session-9: Tasks and Functions

Module M-10: D4-2: Control Flow

• L-1Lesson-10: Control Flow

Module M-11: D5: Process in SV

• L-1Lesson-11: Process in SV

Module M-12: D6: OOPs Concept in System Verilog

• L-1Lesson-12: OOPs Concept in System Verilog

Module M-13: Case Study: Design and Verification of D-FF with Synchronous Reset

• L-1Case Study: Design and Verification of D-FF with Synchronous Reset