2-WEEKS WORKSHOP ON ADVANCE RTL DESIGN AND VERIFICATION

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2-WEEKS WORKSHOP ON ADVANCE RTL DESIGN AND VERIFICATION

Instructor MUKESH SUKLA
Category Workshops
Last Update 10 Oct, 2025
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About The Course

This workshop is designed to enable the learners to understand the fundamentals of digital design and verification.

The Course Curriculam

D1-1: Introduction to VLSI Design and Oppurtunities

Introduction to VLSI Design and Career Opportunities

D1-2: RTL Design Fundamentals

D1-3: Introduction to Design Verification

D2-1: Testbench-Based Verification

D2-2: Design Verification using Intel Quartus Flow

D2-3: System Verilog for Verification

D3-1: RTL Design using Behavioral Model

D3-2: Data Types in System Verilog

D4-1: Tasks and Functions

D4-2: Control Flow

D5: Process in SV

D6: OOPs Concept in System Verilog

Case Study: Design and Verification of D-FF with Synchronous Reset

MUKESH SUKLA

Semiconductor Expert

Ph.D., M. Tech, B.Tech/ Experience (s): 20 Years

14 Courses 199 Students

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₹249 75% Off

Course Information

Course level: Beginner
Instructor: MUKESH SUKLA
Lesson: 13
Last Updated: Oct 10, 2025
Quizzes: 0

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2-WEEKS WORKSHOP ON ADVANCE RTL DESIGN AND VERIFICATION

2-WEEKS WORKSHOP ON ADVANCE RTL DESIGN AND VERIFICATION

About The Course

The Course Curriculam

D1-1: Introduction to VLSI Design and Oppurtunities

Introduction to VLSI Design and Career Opportunities

D1-2: RTL Design Fundamentals

RTL Design using Verilog HDL

D1-3: Introduction to Design Verification

Design Verification Fundamentals

D2-1: Testbench-Based Verification

Testbench Fundamentals

D2-2: Design Verification using Intel Quartus Flow

Design Verification using Intel Quartus

D2-3: System Verilog for Verification

System Verilog for Verification

D3-1: RTL Design using Behavioral Model

RTL Design using Behavioral Model

D3-2: Data Types in System Verilog

Data Types in SV

D4-1: Tasks and Functions

Session-9: Tasks and Functions

D4-2: Control Flow

Lesson-10: Control Flow

D5: Process in SV

Lesson-11: Process in SV

D6: OOPs Concept in System Verilog

Lesson-12: OOPs Concept in System Verilog

Case Study: Design and Verification of D-FF with Synchronous Reset

Case Study: Design and Verification of D-FF with Synchronous Reset

MUKESH SUKLA

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Shopping cart

2-WEEKS WORKSHOP ON ADVANCE RTL DESIGN AND VERIFICATION

2-WEEKS WORKSHOP ON ADVANCE RTL DESIGN AND VERIFICATION

About The Course

The Course Curriculam

D1-1: Introduction to VLSI Design and Oppurtunities

Introduction to VLSI Design and Career Opportunities

D1-2: RTL Design Fundamentals

RTL Design using Verilog HDL

D1-3: Introduction to Design Verification

Design Verification Fundamentals

D2-1: Testbench-Based Verification

Testbench Fundamentals

D2-2: Design Verification using Intel Quartus Flow

Design Verification using Intel Quartus

D2-3: System Verilog for Verification

System Verilog for Verification

D3-1: RTL Design using Behavioral Model

RTL Design using Behavioral Model

D3-2: Data Types in System Verilog

Data Types in SV

D4-1: Tasks and Functions

Session-9: Tasks and Functions

D4-2: Control Flow

Lesson-10: Control Flow

D5: Process in SV

Lesson-11: Process in SV

D6: OOPs Concept in System Verilog

Lesson-12: OOPs Concept in System Verilog

Case Study: Design and Verification of D-FF with Synchronous Reset

Case Study: Design and Verification of D-FF with Synchronous Reset

MUKESH SUKLA

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