6-Days Workshop on Digital Design using Verilog HDL

Module M-3: Verilog HDL Data Types

• L-1L3: Data Types
• Q-1Evaluation-1

Module M-4: Verilog HDL Operators

• L-1L4-1: Operators (PART-1)
• L-2L4-2: Operators (PART-2)

Module M-5: Behavioral Model

• L-1L5: Behavioral Model

Module M-6: Structural Model, Primitives and Port Connectivity Rules

• L-1L6: Structural Model and Primitives

Module M-7: Testbench Fundamentals

• L-1L7: Testbench Fundamentals and Verification Constructs

Module M-8: Quartus Tool Flow

• L-1L8: Quartus Flow

Module M-9: Switch-level Model

• L-1L9: Switch-Level Modeling

Module M-10: System-level Designs

• L-1Digital System Design Fundamentals
• L-2Digital System Design Fundamentals-II

Module M-11: Practice Codes

• L-1Day#1: Practice Codes
• L-2Day#2: Practice Codes for design
• L-3Day#3: Practice Codes
• L-4Day#4: Practice Codes