VLSI Design Engineer - I

Module M-3: Module-3: Advanced Logic Design

• L-1Sequential System Design (PART-2)
• L-2Verilog for Verification: Advance Constructs using Loops
• L-3Finite State Machine (FSM) Fundamentals
• L-4Tasks And Functions
• L-5Switch Level Model
• L-6Arithmetic Blocks

Module M-4: Module-4: System Architecture

• L-1Architecture and Micro-architecture: System Design Examples
• L-2Concept Building: System Design
• L-3ASIC Design Flow
• L-4Design Constraint Fundamentals

Module M-5: Module-5: Logic Synthesis and Performance Analysis

• L-1Design Constraints: SDC Fundamentals
• L-2Synthesis using Genus
• L-3TCL Script-based Synthesis Process
• L-4Standard Cell Characteristics
• L-5Library Fundamentals
• L-6Interconnect and Wire load Model
• L-7RTL and Verification Signoff

Module M-6: Module-6: Hands-on with Block-level Design and Sign-Off

• L-1Register Bank with Data Bus
• L-2Memory Block
• L-3Program Counter
• L-4I2C
• L-58-Bit ALU