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5.00
(3.00)
MUKESH SUKLA
25
Courses
•
400
Students
5.00
(3.00)
Biography
Ph.D., M. Tech, B.Tech/ Experience (s): 20 Years
Courses
Internship on Protocol Design and Verification
8
100h
By
MUKESH SUKLA
In
Digital
Integrated Diploma in VLSI Design (IDVD)
18
By
MUKESH SUKLA
In
ASIC Design
Summer Training on Design Verification using System Verilog
19
200h
By
MUKESH SUKLA
In
Digital
6-Weeks Summer Training on VLSI Design
1
250h
By
MUKESH SUKLA
In
ASIC Design
System Verilog and Protocol Verification
7
200h
By
MUKESH SUKLA
In
ASIC Design
Semiconductor Devices
3
10h
By
MUKESH SUKLA
In
Core Engineering
IETE Sponsored 6-Days Workshop on VLSI Circuits and PCB Design (Hybrid)
0
36h
By
MUKESH SUKLA
In
Workshops
6-Days Workshop on Design Verification using System Verilog and FPGA Validation
16
40h
By
MUKESH SUKLA
In
Workshops
2-WEEKS WORKSHOP ON ADVANCE RTL DESIGN AND VERIFICATION
7
By
MUKESH SUKLA
In
Workshops
Training on VLSI Circuits and PCB Design
27
36h
By
MUKESH SUKLA
In
Analog and Mixed Signal
Python for VLSI Engineers – A Journey towards Automation
22
72h
By
MUKESH SUKLA
In
Programming and Scripting
Circuit Design and Verification Engineer – I
4
By
MUKESH SUKLA
In
ASIC Design
5.00
(1)
C PROGRAMMING FOR VLSI ENGINEERS
10
45h
By
MUKESH SUKLA
In
Programming and Scripting
Linux and Shell Scripting for VLSI Engineers
19
40h
By
MUKESH SUKLA
In
Programming and Scripting
5.00
(2)
TCL Script for VLSI Engineers
30
By
MUKESH SUKLA
In
Programming and Scripting
Bootcamp Program on Digital Design using Verilog HDL
75
12h
By
MUKESH SUKLA
In
ASIC Design
4-Weeks Winter Training on RTL Design
29
100h
By
MUKESH SUKLA
In
Digital
VLSI Design Engineer – I
31
100h
By
MUKESH SUKLA
In
ASIC Design
6-Days Workshop on Digital Design using Verilog HDL
22
40h
By
MUKESH SUKLA
In
Workshops
Design Verification using System Verilog and Protocol Fundamentals
10
150h
By
MUKESH SUKLA
In
ASIC Design
Advanced Design Verification using UVM
2
100h
By
MUKESH SUKLA
In
Digital
Foundations of System-on-Chip Design and Custom Layout Techniques for Healthcare Applications
2
By
MUKESH SUKLA
In
Workshops
MNDCS-2026 Invited Talk
0
2h
By
MUKESH SUKLA
In
Workshops
Advanced RTL Design and Verification using System Verilog (Level-1)
0
200h
By
MUKESH SUKLA
In
ASIC Design
,
Workshops
VLSI Sample Test (VST) Series
38
By
MUKESH SUKLA
In
Core Engineering
